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Silicon-verified reference flows from RTL to GDSII are available to Common Platform customers from our major EDA partners, Cadence Design Systems and Synopsys with physical verification solutions offered by Mentor Graphics. Complete design flows are available for generic and low power at 90nm and for low power at 65nm with integrated solutions for timing, power, area, and signal integrity.

The Common Platform alliance partners work with each vendor to validate data models and flows and ensure the flow’s quality-of-results and ease-of-use.

The reference flows can be extended to address specific design requirements and also are linked to critical DFM tools and methodologies.

Reference Flows