Common Platform
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Extensive technical discussions and exchange of design practices with our library partners, ARM and Virage Logic, have resulted in a set of standard cell libraries highly optimized for each target process node. These libraries cover a wide variety of applications with versions to support high performance, optimized area, and low power. Because the footprints are identical, multi-vt libraries are interchangeable with each other (within the same process node). We also support over-drive library for the highest speed and multi-condition characterization for high accuracy.

Further, our library offerings have gone through full DFM verification.

Standard Cell

We offer a broad range of standard cell libraries:

  • Very high performance
  • Performance & density optimized
  • Low Power & high density
  • Multiple VT options
  • Variety of voltage option

General I/O

We offer a broad set of I/O interfaces for a wide range of application types:

  • 3.3V LVTTL
  • 1.8V/2.5V CMOS (2.5V/3.3V Tolerant
  • 2.5V SSTL DDR1 and 1.8V SSTL DDR2
  • 1.5V HSTL
  • Many other options
  • Input Disable Function
  • Controllable Pull-Up/Down
  • Competitive pitch

Memory Compilers

A full range of characterized silicon-verified memory compilers are offered:

  • High density single port SRAM
  • Performance single port SRAM
  • Dual ports DRAM compiler
  • 1P/2P register file compiler
  • VROM

Low Power Library

Category Components 90nm LP 65nm LP 45nm LP
Std Cell Metro + Power Management Kit
Advantage + Power Management Kit
Advantage HS + Power Management Kit
Memory Metro SP Sync SRAM Memory Compiler with Flex Repair
Advantage SP Sync SRAM Memory Compiler with Flex Repair
Metro DP Sync SRAM Memory Compiler with Flex Repair
Advantage DP Sync SRAM Memory Compiler with Flex Repair
Metro Via Programmable ROM Compiler
Advantage Via Programmable ROM Compiler
Metro Dense SP Sync SRAM Memory Compiler with Flex Repair
Advantage Dense SP Sync SRAM Memory Compiler with Flex Repair
Metro 1P Register File Compiler with Flex Repair
Advantage 1P Register File Compiler with Flex Repair
Metro 2P Register File Compiler with Flex Repair
Standard I/O Metro GPIO Inline
Metro GPIO Staggered
Metro SSTL2, SSTL18, HSTL Inline
Metro SSTL2, SSTL18, HSTL Staggered

Performance Library

Category Components 90nm G 65nm G 45nm G
Std Cell Advantage + PMK1
Advantage HS + PMK1
Memory Advantage SP Sync SRAM Memory Compiler with Flex Repair
Advantage DP Sync SRAM Memory Compiler with Flex Repair
Advantage Via Programmable ROM Compiler
Advantage Dense SP Sync SRAM Memory Compiler with Flex Repair
Advantage SP Register File Compiler with Flex Repair
Advantage 2P Register File Compiler with Flex Repair
Standard I/O GPIO Inline
GPIO Inline
GPIO Inline
GPIO Staggered
GPIO Inline
GPIO Staggered
SSTL25, SSTL18, HSTL Inline
SSTL25, SSTL18, HSTL Staggered
GPIO Inline
GPIO Staggered