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The Common Platform works with a robust ecosystem of design enablement partners that provide consistent and reliable support for designs targeting any of our manufacturing facilities. We work with these partners to offer comprehensive Digital and Mixed Signal IPs portfolio. These IPs are classified in three levels, IP design kits, IP silicon validated, and IP-productions.

 

Reference Design Flows Design Compatibility
Design Center Collaborators
Libraries and IP
Technology Design Kits GDSII Compatibility
Design Manual SPICE Models Process and Manufacturing
Compatibilty
90nm, 65nm, 45nm
Process Platforms



In conjunction with our fab sync and MPW program, IPs, which are validated by one of the Common Platform alliance partners, are able to work in any of the other Common Platform alliance partners fabs. This can reduce the time to market for our customers when multiple sourcing of wafers are required. There is no need to re-Silicon Validate the IP in the other fabs. We also work with our partners very closely on technical and business aspects, providing our customers an advantage of having the best technical solutions available in a seamless fashion.

Examples of Common Platform IP:

  • Special I/O
    • SerDes, USB 2.0
    • SATA, SATA Gen2
    • PCI, PCI Express
    • Other customer I/O
  • XUAI
  • PLL
  • ADC
  • DAC, Video DAC


IP Validation Levels

Level 1 - IP with Design Kit

Level 2 - Silicon Validated

Level 3 - IP in Production



Reference Design Flows The Common Platform technology
is supported by a robust design
enablement ecosystem
Design Service Partners
Libraries and IP
Technology Design Kits
Design Manual SPICE Models
90nm, 65nm, 45nm Process Platforms

 

Level 1 - IP with Design Kit

This is the minimum criteria for an IP to be listed on the Common Platform website or to be included in any promotional material. To qualify for this level, the IP partner must meet the following criteria.

  1. The partner must provide deliverable as listed. (Please contact your local Common Platform ecosystem partner for a detailed listing)
    1. Front end and back end views
    2. Datasheet
    3. Application note
  2. IP Partner to provide list design flow validated (Common Platform reference flow)

Level 2 - Silicon-validated IP

At this level, the IP has been either silicon validated on a MPW or in a customer design. The IP partner is required to provide supporting data. These reports may include but are not limited to the following:

  1. Measured silicon data versus datasheet.
  2. Measured silicon data versus simulation.
  3. ESD Test Result.

Level 3 - IP in Production

This is the highest level of qualification, for IP which has been used in a production design. The IP partner is required to provide the IP name, process ID, and verification from the customer using the IP to any one of the Common Platform alliance partners, Chartered, IBM or Samsung. A certificate listing the IP name, process ID, process revision, and date is to be provided to the IP vendor. The certificate is meant as a record only of IP in production. It does not guarantee that the IP will work in every design, or when the IP is placed in the new design.

 

For more information or if you would like to submit your solution for validation please send an email to validation@commonplatform.com